RFQ / BOM 0 Entrar / Registro

Selecione seu local

imagem do usuário

What are the reasons for the damage of the MOSFET?

Hardware design
setembro 30, 2020 by Margo 1086

The younger brother is a beginner in electronics, and often damages the MOSFET when designing the circuit. What are the reasons for the damage to the MOSFET?

Todos os comentários

user image

Yuri postado em September 30, 2020

One: avalanche damage

If a surge voltage exceeding the rated VDSS of the device is applied between the drain and the source, and the breakdown voltage V(BR)DSS is reached (different according to the breakdown current), and a certain amount of energy is exceeded, damage will occur.

The flyback voltage generated when the switching operation of the dielectric load is turned off, or the peak voltage generated by the leakage magnetic inductance exceeds the rated withstand voltage of the drain of the power MOSFET and enters the breakdown zone to cause damage, which will cause avalanche damage.

0
user image

Lars postado em September 30, 2020

The second type: thermal damage to the device

Caused by heat generated beyond the safe area. The cause of heating is divided into two types: DC power and transient power.


DC power reason: heat caused by loss caused by external DC power


●On-resistance RDS(on) loss (RDS(on) increases at high temperature, resulting in increased power consumption at a certain current)


●Loss caused by leakage current IDSS (very small compared with other losses)


Transient power reason: plus one-shot pulse

0
user image

Janna postado em September 30, 2020

The third type: built-in diode destruction

When the parasitic diode formed between the DS terminals operates, the parasitic bipolar transistor of the power MOSFET operates during Flyback, which causes the diode to break down.

0
user image

Jessy postado em September 30, 2020

Fourth: damage caused by parasitic oscillation

This damage method is especially prone to occur in parallel


Parasitic gate oscillation occurs when power MOS FETs are connected in parallel without inserting gate resistance. When the drain-source voltage is repeatedly turned on and off at high speed, this parasitic oscillation occurs on the resonant circuit formed by the gate-drain capacitance Cgd (Crss) and the gate pin inductance Lg. When the resonance condition (ωL=1/ωC) is established, a vibration voltage far greater than the driving voltage Vgs(in) is applied between the gate and the source, and the gate is destroyed due to the exceeding of the rated voltage between the gate and the source, or The vibration voltage when the drain-source voltage is turned on and off causes positive feedback due to the overlap of the gate-drain capacitance Cgd and the Vgs waveform, which may cause oscillation damage due to malfunction.

0

Escreva uma resposta

Você precisa fazer login para responder. Entrar | Registro