LAN91C96-MS

The LAN91C96 Ethernet controller comes in two different packages as mentioned in the datasheet: 100 PIN TQFP Package and 100 PIN QFP Package. The 100 PIN TQFP Package has dimensions and specifications listed on Page 124 . Both packages have different overall package heights, body thickness, lead frame thickness, lead foot length, lead pitch, lead foot angle, lead width, lead shoulder radius, lead foot radius, and coplanarity.

The LAN91C96 is described as a Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet.

The LAN91C96 Ethernet controller offers the following key features as listed in the datasheet: - Non-PCI Single-Chip Ethernet Controller - Fully Supports Full Duplex Switched Ethernet - Supports Enhanced Transmit Queue Management - 6K Bytes of On-Chip RAM - Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards - Automatic Detection of TX/RX Polarity Reversal - Enhanced Power Management Features - Supports "Magic Packet" Power Management Technology - Simultasking Early Transmit and Early Receive Functions - Enhanced Early Transmit Function - Receive Counter for Enhanced Early Receive - Hardware Memory Management Unit - Optional Configuration via Serial EEPROM Interface (Jumperless) - Supports single +5V or +3.3V VCC Designs - Supports Mixed Voltage External PHY Designs - Low Power CMOS Design - Integrated Ethernet controller mapped entirely in I/O space - Built-in 6kbyte RAM for packet storage - Memory Management Unit parameters include 6kbytes RAM size, 24 max. number of pages, 24 max. number of packets, 6 max. pages per packet, and 256 bytes page size - Logical addresses for RAM access divided into TX area and RX area - TX area for loading packets into memory before queuing in TX FIFO and examining transmit completion status - RX area for accessing receive packet data and status information - Address pointer register for specifying logical address with automatic increment on accesses