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IC MTR DRV MULTIPHAS 6-95V 48QFN
• 9 to 100-V, Triple Half-Bridge Gate Driver
– Optional Integrated Buck Regulator
– Optional Triple Low-Side Current Shunt Amplifiers
• Smart Gate Drive Architecture
– Adjustable Slew Rate Control For EMI Performance
– VGS Handshake and Minimum Dead-Time Insertion to Prevent Shoot-Through
– 50-mA to 1-A Peak Source Current
– 100-mA to 2-A Peak Sink Current
– dV/dt Mitigation Through Strong Pulldown
• Integrated Gate Driver Power Supplies
– High-Side Doubler Charge Pump For 100% PWM Duty Cycle Control
– Low-Side Linear Regulator
• Integrated LM5008A Buck Regulator
– 6 to 95-V Operating Voltage Range
– 2.5 to 75-V, 350-mA Output Capability
• Integrated Triple Current Shunt Amplifiers
– Adjustable Gain (5, 10, 20, 40 V/V)
– Bidirectional or Unidirectional Support
• 6x, 3x, 1x, and Independent PWM Modes
– Supports 120° Sensored Operation
• SPI or Hardware Interface Available
• Low-Power Sleep Mode (20 µA at VVM = 48-V)
• Integrated Protection Features
– VM Undervoltage Lockout (UVLO)
– Gate Drive Supply Undervoltage (GDUV)
– MOSFET VDS Overcurrent Protection (OCP)
– MOSFET Shoot-Through Prevention
– Gate Driver Fault (GDF)
– Thermal Warning and Shutdown (OTW/OTSD)
– Fault Condition Indicator (nFAULT)
• 3-Phase Brushless-DC (BLDC) Motor Modules
• Fans, Blowers, and Pumps
• E-Bikes, E-Scooters, and E-Mobility
• Power and Garden Tools, Lawn Mowers
• Drones, Robotics, and RC Toys
• Factory Automation and Textile Machines
The DRV835x family of devices are highly-integrated gate drivers for three-phase brushless DC (BLDC) motor applications. These applications include fieldoriented control (FOC), sinusoidal current control, and trapezoidal current control of BLDC motors. The device variants provide optional integrated current shunt amplifiers to support different motor control schemes and a buck regulator to power the gate driver or external controller.
The DRV835x uses smart gate drive (SGD) architecture to decrease the number of external components that are typically necessary for MOSFET slew rate control and protection circuits. The SGD architecture also optimizes dead time to prevent shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by MOSFET slew rate control, and protects against gate short circuit conditions through VGS monitors. A strong gate pulldown circuit helps prevent unwanted dV/dt parasitic gate turn on events.
Various PWM control modes (6x, 3x, 1x, and independent) are supported for simple interfacing to the external controller. These modes can decrease the number of outputs required of the controller for the motor driver PWM control signals. This family of devices also includes 1x PWM mode for simple sensored trapezoidal control of a BLDC motor by using an internal block commutation table.
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