TC358860XBG

The TC358860XBG chip can receive up to 17.28 Gbps of video stream through its four eDP main link lanes, which can toggle at different speeds .

The standards followed by TC358860XBG include restrictions on product use set by Toshiba Corporation and its subsidiaries and affiliates. These restrictions state that Toshiba reserves the right to make changes to the information in the document and related product without notice. Additionally, reproduction of the document and any information therein is not allowed without prior written permission from Toshiba, and even with permission, reproduction is only permissible if done without alteration or omission. TC358860XBG is housed in a 5.0 mm by 5.0 mm size package with a 0.5mm ball pitch. The package details include a solder ball pitch of 0.50 mm, solder ball height of 0.25mm, package dimension of 5.0 x 5.0 mm2, and a package height of 1.2mm maximum.

TC358860XBG can handle input video streams with bandwidth requirements between 4 Gbps and 8 Gbps by performing left-right line split and using dual DSI links for outputting the video data stream. Additionally, it provides a compression engine that compresses video data with a 2-to-1 ratio, allowing it to receive 4K @60fps video streams at eDP Rx, compress them, and send them out to a dual DSI link 4K panel for display. A decompression engine is expected in the DSI panel.